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Author Topic: SNES math register / timing questions  (Read 494 times)
Kejardon
Guest
« on: November 18, 2006, 10:21:36 pm »
I've been poking around in some of Nintendo's code, and they often STA $4203 then LDA $4216 only 6 cycles later (3 NOPs). I'm *guessing* this is because there's an additional 2 cycles after the LDA $4216 is read but before the value from $4216 is actually read? If so, can someone point me to docs that explain that kind of timing for opcodes or something?
They also have a LDA $4216 only 5 cycles after the STA $4203, but that's part of an RNG, so I'm guessing that's meant to be a messed up number. Tongue Either that or multiplication by 5 is guaranteed to be done within 5 cycles (NOP + REP #$20)  (or 7 counting the delay between LDA and actual read, I guess). Any notes on this either?
Nightcrawler
Guest
« Reply #1 on: November 19, 2006, 12:51:02 pm »
The official documentation states:

When using $4202/$4203 for multiplication, the operation will start as soon as $4203 is written and completed after an 8 machine cycle period.

When using $4204/$4205/$4206 for division, the operation will start as soon as $4206 is written and completed after an 16 machine cycle period.

It has been observed however that several ROMs will not properly use these registers. If you don't wait long enough, you can can get an undetermined(nobody knows all the steps taken yet) intermediate answer which can still work correctly with your code depending on the numbers used. The machine cycle waits would be a completion time for the longest operation. If you used smaller number, your effective answer would complete before that time.
Kejardon
Guest
« Reply #2 on: November 19, 2006, 06:03:44 pm »
k.
You kinda skipped my first question though. :/ Is there extra delay between the start of the opcode and the time the register is actually read? Or maybe even extra delay after $4203 is written to but before STA is done?
Nightcrawler
Guest
« Reply #3 on: November 19, 2006, 07:20:46 pm »
Quote from: Kejardon on November 19, 2006, 06:03:44 pm
k.
You kinda skipped my first question though. :/ Is there extra delay between the start of the opcode and the time the register is actually read? Or maybe even extra delay after $4203 is written to but before STA is done?

Yes. Some of the machine cycles that the opcode takes up is used to set the address on the bus before it can read it. So, yes, there is some delay after the start of the opcode before it actually reads the value from that register.

I can't tell you how many cycles that is because I don't have the information handy and it can vary depending on the region accessed and some hardware settings.
DMV27
Guest
« Reply #4 on: November 19, 2006, 07:56:07 pm »
LDA $4216 has 3 cpu cycles before the read from $4216. This document lists all of the opcode timings:

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Kejardon
Guest
« Reply #5 on: November 19, 2006, 09:50:58 pm »
Great! Thanks for the help Cheesy
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